测试技术

—— TEST TECHNOLOGY ——

Improving Wafer-Level S-parameters Measurement Accuracy and Stability with Probe-Tip Power Calibration up to 110 GHz for 5G Applications

Fig.11.S-parameter post-calibration stability performance with and without Probe-Tip power calibration,monitoring Extracted Inductance of a 1ps line over time.

27

2023

/

12

improving-wafer-level-s-param-eumc-2019-sia

An accurate and stable wafer-level 110 GHz system is needed to support measurements of devices and circuits for 5G applications.A novel method of probe-tip power calibration with S-parameter calibration has been proposed in this paper.The new instrumentation technique,named Choon’s probe-tip power calibration method is demonstrated to improve DC biasing accuracy,S-parameters measurement consistencies and accuracy as well as post-calibration stability.Using this probe-tip power calibration method,110 GHz system calibration stability is improved from 10 minutes to more than 4 hours,greatly improving the measurement throughput of such test setup,making power calibration mandatory for achieving accurate wafer-level S-parameters measurements.

27

2023

/

12

IMS2010-MicroApps-WinCalXE-TwoTierCal

Two Tier Calibration of a Vector Network Analyzer is a technique that allows two calibration error sets to be combined into one

27

2023

/

12

Optimized Impedance Standard Substrate Designs for Dual and Differential Applications

Abstract--Optimized dual signal Impedance Standard Substrate(ISS)designs are demonstrated.The optimal designs had loop-under grounds,were selected for minimum deviation from lumped element behavior and used mode dampening structures.A comparison of existing design approaches is given and the quality of the designs is illustrated to 50GHz.

27

2023

/

12

Test Setup Optimization and Automation for Accurate Silicon Photonics Wafer Acceptance Production Tests

Yurii A.Vlasov and Sharee J.McNab,“Losses in single-mode silicon-on-   insulator strip waveguides and bends”,Optical Express,Vol.12,Issue 8,pp.1622-1631,2014

27

2023

/

12

Validation of On-Wafer Vector Network Analyzers

ƒFuture work will include comparing on-wafer VNAs employing different calibration algorithms   See it.Touch it.Measure it.®

27

2023

/

12

Validation of On-Wafer VNA Systems

Abstract — The case study described in this paper applies a known vector network analyzer comparison technique to an on- wafer measurement environment. The purpose is to investigate and expand upon this technique’s applicability for use in validating an on-wafer VNA system of unknown accuracy by comparing it to an on-wafer VNA system of trusted accuracy. The technique involves taking calibrated S-Parameter measurements with each system over a set of validation devices and calculating the measurement differences between the two systems. These differences are then compared to the estimated repeatability uncertainty bounds of the two VNAs in order to validate or invalidate the unknown system’s capabilities. Results and limitations of this procedure are discussed.

17

2023

/

11

< 1 >